If you’ve seen either my VHDL or Verilog video,
you’ll know that Logisim Evolution warned me about having gated clocks
in my CPU design. It said that
there is a possibility the design won’t work right in an FPGA due to the gated
clocks. So, in this video, I’ll remove the gated clocks. And, you’ll see that
there is an unexpected benefit of doing this. The term “gated clocks” means that components
with a clock line, such as registers, counters, and flip-flops, are clocked
by the result of a gate, such as an AND, rather than being clocked by the
main clock. Gate delays can
then maybe cause the component to be triggered at the wrong time. I now clock all registers and counters by
the main clock. They are still
triggered by the same lines as before, but now, the trigger only takes effect
on the specified edge of the main clock. This caused something seemingly
strange. The Program Counter and Instruction Register
now have to be triggered by the falling edge of the clock rather than
the rising edge as before. Now all
registers and counters are falling edge, which in my opinion makes the design
cleaner. Since the clocking was changed, I wondered
if the MUX on the Program Counter’s input can now be put back in. It was in my original design many years
ago but had to be taken out to make the JUMP instruction work in Logisim, which
then sacrificed the indirect jump instructions. I had to put in a
new control line to select the MUX line. The indirect jump instruction
is now implemented and works. By the way, there are technically still gated
clocks. The fetch-execute
flip-flops aren’t triggered by the main clock. However, the D flip-flop is
triggered by the Start button. This seems unavoidable, and shouldn’t be a
problem since it only happens at the start. The J-K flip-flop is triggered by
the AND, but I don’t think this would be a problem either. It seems to me that
it’s coordinating all the path enables, so to speak, but the clocking of the
various memory components is still performed by the main clock. And here’s the new design implemented with
the original Logisim. Since some viewers who have seen my other
videos might be bored with the same running programs, I’ve written some new
ones. These are various numerical
computation programs. First, the ubiquitous Fibonacci sequence. Personally, I
don’t understand the fascination with it, but it seems to be a standard “Hello
World” type of thing, so why not do it? The second one, computes all the prime
numbers up to a 1000. And the third one computes Pi to 800 digits. It took too
long, so I cut it off early. These video sections are sped up in order
to not take up much time. They take much longer than this to compute
in Logisim. And here’s a bonus fourth program I added
later. It computes factorials from 1
factorial to 365 factorial. I’ll once again cut it short. By the way, I used
this version of my CPU and computer because without some of my extra features
and with running on original Logisim, it is faster. I
wrote a simulator for my CPU. This text-based simulator runs a lot faster
than Logisim since it doesn’t have to simulate
the electronics. You can see all of
the Pi computation. Probably in my next video, I’ll show the graphical
version of my simulator. Here’s the program that does the numerical
computations. I created settings
in notepad++ for my CPU’s assembly language, so the assembler directives,
comments, assembly mnemonics, and data have different colors. And notepad++ can
correctly predict what you’re trying to type. More readable mostly C code
appears in the comments. Here’s the new instruction set. The indirect jump now works. The indirect-
indirect jump still doesn’t work, but because of a different reason which was
mentioned in my first Logisim video. So, now, there are new indirect versions
of the conditional jumps. And a totally new instruction – STOREAIND. It is the
store version of the LOADAIND instruction. It stores the A value in a memory
location pointed to by Y. This instruction was needed in the new numerical
computation programs. Luckily, the necessary paths were already
in the design, so I just needed to turn on the right paths
for this new instruction. So, the
control ROM had to be edited, adding the new instructions. To test the new jump instructions, I created
an all indirect jump version of my other program. And here’s just the new program. This version was shown
running correctly earlier in this video. The obvious question now is – does this new
design still work in VHDL and Verilog? Well, one problem did come up because when
the main clock is used, Evolution uses a “clock tree”. Here’s the waveforms of the bits of the clock
tree. Dealing with this clock tree all throughout
the CPU is a lot harder than dealing with just a normal on-off 1-bit clock. I couldn’t manage to get it to
work with this clock tree. Maybe in an actual FPGA it would work, I don’t
know, but in the VHDL and Verilog compilers I use,
it didn’t work. My solution to this problem was to temporarily
put in a buffer between the main clock and my CPU. This will cause Evolution to not use the clock
tree past the buffer when generating the VHDL and Verilog
code. The next step is to find
the buffer in the generated code, and then take it out. Note the 36 and 39
lines. Since line 36 only appears once, the easiest
way is to change the 36 to 39, which means the main clock now is connected
to line 39. Here’s the code differences between the temporary
buffer version and the clock tree version. As you can see, the VHDL and Verilog versions
still work. I’m glad I took out the gated clocks, and
I’m also glad my original design years ago has been proven to be more correct
than I thought.

My CPU: Goodbye Gated Clocks! Hello Indirect Jumps (Now With More Programs)
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2 thoughts on “My CPU: Goodbye Gated Clocks! Hello Indirect Jumps (Now With More Programs)

  • October 24, 2017 at 2:03 pm
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    I got a problem: i build an GPU (or to be more precice just an rasterizer that converts a triangle into pixels). But it takes half a minute to draw a single triangle, because my computer can only simulate 1000tps. Is there a way to speed things up? (Other than reducing the size of the screen). btw. im using standart logicsim.

    Reply
  • October 24, 2017 at 6:16 pm
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    you is king.

    Reply

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